1. Field of the Invention
The present invention is concerned with random access memories of the type fabricated on a monolithic semiconductor chip using insulated gate semiconductor field effect transistor technology, and more particularly relates to an impedance device for conducting extremely low currents from a drain supply node through the channel of an insulated gate field effect transistor in a memory cell.
2. Description of the Prior Art
A digital memory must contain a discrete physical storage cell which is capable of being set by an external signal into one of two distinct states for each bit of the computer word to be stored. The cell must remain in this set state indefinitely or until it is changed to the other state by another external signal. The two distinct states of a storage cell can be naturally occurring states which require no external energy source to be maintained. It is also possible to use storage elements of the volatile type which require external energization to maintain the stored state. A well-known example of such storage elements is the bistable circuit which employs semiconductor devices. These devices require a continual or permanent application of power in order to prevent deterioration or a complete loss of the stored information.
Large scale integration (LSI) techniques have brought about the construction of large arrays of such storage elements on a single chip of silicon. These storage cells, typically using MOS technology, consist of multicomponent circuits in a conventional bistable configuration. Storage of this type is inherently volatile since the semiconductor bistable elements require a constant source of power to maintain the stored information. In some applications, it is essential that the data should not be irretrievably lost due to an interruption of power. In those applications, standby power is provided by means of batteries which are operably connected to power supply nodes of the memory system to supply power in the event of an inadvertent interruption of essential d.c. power, and to supply power during operation of the memory in the standby mode.
The immediate advantages of semiconductor storage devices are the high packing density and low power requirements. The insulated gate MOS transistor has been particularly exploited in this application area since it requires less substrate area (thereby increasing the packing density) and operates at very low power levels. A well known memory cell circuit arrangement which utilizes insulated gate MOS field effect transistors is the cross-coupled inverter stage as disclosed in U.S. Pat. No. 3,967,252. In that circuit the gates of a pair of MOSFET transistors are cross coupled to a true data node and a complementary data node. Information stored within the cell is maintained by impedance means which are connected to the data nodes to maintain the potential at the gate of the transistors at a predetermined level which corresponds to the logic content of the cell. Each inverter of the cell consists of a driver transistor and a load impedance means. In the circuit shown in that reference, the load impedance means comprises a MOSFET transistor. In earlier circuits, impedance means comprising diffused resistors typically exhibiting 10 to 20 ohms per square were utilized. However, use of the MOSFET transistor has been preferred since it is capable of providing 20,000 ohms per square, giving practical resistance values of the order of 100,000 to 200,000 ohms.
By using less surface area than a conventional diffused resistor, MOS technology allows more complex circuitry on a single monolithic chip than would otherwise be possible. For low current load device applications, the depletion MOSFET transistor having its gate tied to its source occupies less substrate area. However, for very low current load applications, the depletion transistor with gate tied to source occupies several square mils of area in the microampere load range.
In the static random access memory cells shown in U.S. Pat. No. 3,967,252, there are two cross-coupled inverters and two transfer resistors, i.e., two load devices and four transistors. In a 1K static RAM, the 1,024 memory cells take up approximately 40 percent of the total chip area, while in the 4K static RAM the 4,096 memory cells occupy slightly more percentage of the chip. In order to keep the chip area as small as possible and the power consumption as low as possible, the two load devices in the static cell of each inverter should be relatively small in area and provide extremely low current. One drawback to the use of the depletion transistor for the load device is that its body effect due to back gate bias generally increases as the physical size of the active area is reduced. A further drawback to the use of the MOS device as the load resistor is that the resistance exhibited by the device is inherently limited by its body effect associated with the source-to-substrate reverse-bias voltage. Although this arrangement will provide practical resistance values on the order of 100,000 to 200,000 ohms, in some extremely low power consumption applications it is desirable to provide load devices exhibiting a resistance in the one megohm to 100 megohm range.